This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No.H11-070879, filed on Mar. 16, 1999 the entire contents of which are incorporated herein by reference.
This invention relates to a synchronous semiconductor memory device such as a synchronous DRAM, etc. in which data read and write operations are synchronously controlled by clock signals.
In a synchronous DRAM (SDRAM), commands and/or addresses are taken thereinto in synchronism with a clock signal and read/write operations of data are carried out in accordance with read/write control signals. For example, at the time of data read operation, data on a bit line of a memory cell array is selected by a column decoder and is transferred to a data line. At this time, in the column decoder controlled by the clock signals, a column select clock signal corresponding to an established internal column address is supplied thereto and a column select line for transferring the selected data on the bit line to the data line is caused to be active.
For a time period during which an address is taken in after a READ command is established and is decoded so that internal column address is established, there exists a predetermined delay time because data is passed through many gates. The number of gate stages of the clock system to generate a column control clock signal for allowing a column select signal to be active in accordance with the a command from an internal clock signal generated by taking an external clock signal thereinto is smaller than that of the above-described address system. Accordingly, in order that the column control clock signal is caused to be generated after the internal column address is established, an approach where a predetermined delay is given to the generation path of column control clock signal.
In more practical sense, the delay time from the time when the external address is taken in to the time when the internal column address is established and the delay time for generating the column select clock signal in response to the READ command are both determined with rising edge of the clock signal being as a reference timing. If a delay time of the column select clock signal is adjusted in order that the column select clock signal is generated substantially simultaneously with establishment of the internal column address and is delivered to the final stage of the column decoder, an access time from command input to data output becomes minimum.
However, in practice, since transfer paths for address and clock signal are different as described above, it is difficult to optimumly carry out timing adjustment. For this reason, such an approach has been generally carried out to give delay time longer than the internal column address establishment time so that erroneous column selection is securely prevented. This constitutes the cause to impede more shortening of access time.
In addition, when an order of timings of the internal column address establishment and of generation of the column select clock signal are reversed because of any causes such as variations in process, even if the period of clock signal delivered is elongated to elongate the cycle time, the above-supplied timing relationship will not be changed, resulting in that there is no relief measure. This is because the time required for establishment of the internal column address and the time required for generation of the column select clock signal are both determined with rising edge of clock signal being as reference as described above.